1. Field of the Invention
The present invention relates generally to nonvolatile random access memories and more specifically to a magnetic random access memory using a magnetoresistance element.
2. Description of the Related Art
U.S. Pat. No. 5,748,519 discloses a magnetic RAM in which magnetic memory cells are each comprised of a giant magnetoresistance element and organized into first and second array portions, In each row of the first array portion, the GMRs are connected in series between a row transistor and a first common output line. Likewise, in each row of the second array portions, the GMRs are connected in series between a row transistor and a second common output line. During a read mode, a current is produced in the GMRs of a selected row of the first cell array portion as well as in the GMRs of the corresponding row of the second cell array portion. One of the cell array portions is used to produce a reference voltage. The voltage developed on each common output line is proportional to the total value of the resistances of the series-connected memory cells. A differential amplifier is connected to the first and second common lines to produce an output voltage representing the difference between the voltages developed on the first and second output lines. However, parasitic elements arise from the physical separation of the cell array into the two array portions. Therefore, if variability exists in the operating characteristics of the magnetoresistance elements of the memory it is difficult to implement a magnetic RAM having a sufficient amount of operating margin, In addition, since the total resistance of a selected row contributes to a significant portion of the voltage developed at the common output line, the amount of the voltage contributed by a memory cell of the selected row is small. As a result, the prior art magnetic RAM is less tolerant of cell variability and noise. The problem could be overcome only at the cost of an increase in the resistance of each GMR element, which would require an increase both in power consumption and memory chip size. Furthermore, the total value of the resistances of each selected row inherently includes the turn-on resistance of each row transistor. Since the GMR is a type of device whose resistance is of the same order of magnitude as the resistance of the associated line, the voltage drop contributed by the row transistor and the associated line resistance to the output voltage cannot be ignored, requiring precision sense amplifiers.
U.S. Pat. No. 5,640,343 discloses a magnetic memory array. Each memory cell consists of a magnetic tunnel junction (TMR) element and a diode electrically connected in series. However, a paper titled xe2x80x9cBias Voltage Dependence of Tunneling Magnetoresistance and Annealing Effect in Spin Dependent Tunnel Junctionsxe2x80x9d, J. J. Sun et al, Journal of Magnetics Society of Japan, Vol. 23, No. 1-2, pages 55-57, describes that as the voltage across the tunnel junction increases the magnetoresistance (NR) ratio decreases due to the known bias effect, and hence precision sense amplifiers would be required to detect voltage variations. Further, the tunneling magnetoresistance element cannot tolerate high voltages as described in a paper under the title of xe2x80x9cObservation and analysis of breakdown of magnetic tunnel junctionsxe2x80x9d, W. Oepts, et al, Journal of Magnetism and Magnetic Materials Vol. 198-199, pages 164-166. The application of a high voltage across a tunneling magnetoresistance element would break down the tunnel barrier and shorten its lifetime.
It is therefore an object of the present invention to provide a magnetic random access memory tolerant of variability of the operating characteristics of magnetoresistance elements and capable of operating with a sufficient margin of allowance.
A second object of the present invention is to provide a magnetic random access memory capable of precision readout operation by compensating for the voltage drop caused by the line resistance and transistor""s turn-on resistance connected in series.
A third object of the present invention is to provide a magnetic random access memory capable of high speed readout operation by simultaneously reading stored information from a plurality of memory cells connected to the same word line.
A fourth object of the present invention is to provide a magnetic random access memory using tunneling magnetoresistance elements in the memory cells capable of preventing the breakdown of their tunnel barrier and their bias effect of the tunneling magnetoresistance elements.
A fifth object of the present invention is to provide a low power consumption magnetic random access memory by utilizing energy stored on capacitors.
According to a first aspect, the present invention provides a magnetic random access memory comprising a plurality of word lines, a plurality of sense lines, a matrix array of memory cells, each memory cell being located on an intersection of a corresponding one of the word lines and a corresponding one of the sense lines, each memory cell including a magnetoresistance element and a switching element which establishes a connection between the corresponding sense line and the magnetoresistance element when the corresponding word line is addressed. A plurality of sense circuits respectively correspond to the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and discharging energy stored in the capacitive element when the corresponding sense line is addressed. A plurality of voltage control elements are respectively connected in the sense lines for maintaining the sense lines at constant lower voltages regardless of higher voltages respectively produced by the sense circuits.
According to a second aspect, the present invention provides a magnetic random access memory comprising a plurality of word lines, a plurality of pairs of sense lines, and a matrix array of memory cells, each memory cell being located on an intersection of a corresponding one of the word lines and a corresponding one of the pairs of the sense lines, each memory cell including a first magnetoresistance element and a first switching element which establishes a first connection between a first one of the corresponding pair of sense lines and the first magnetoresistance element when the corresponding word line is addressed. Each memory cell further includes a second magnetoresistance element and a second switching element which establishes a second connection between a second one of the corresponding pair of sense lines and the second magnetoresistance element when the corresponding word lines is addressed. A plurality of sense circuits respectively correspond to the pairs of sense lines, each sense circuit including a first capacitive element connected to a first one of the corresponding pair of sense lines and a first switching element for applying a voltage to the first capacitive element and discharging energy stored therein when the first one of the corresponding pair of sense lines is addressed. Each sense circuit further includes a second capacitive element connected to a second one of the corresponding pairs of sense lines and a second switching element for applying a voltage to the second capacitive element and discharging energy stored therein when the second one of the corresponding pair of sense lines is addressed simultaneously with the first one of the corresponding pair of sense lines. A plurality of pairs of voltage control elements are respectively connected in the pairs of sense lines for maintaining all the sense lines at constant lower voltages regardless of higher voltages respectively produced by the sense circuits. A plurality of differential amplifiers may be provided respectively corresponding to the sense circuits, each of the differential amplifiers producing a difference output representative of the difference between voltages developed by the first and second capacitive elements.
According to a third aspect, the present invention provides a magnetic random access memory comprising a first plurality of word lines, a second plurality of word lines, a first plurality of sense lines, a second plurality of sense lines, a first plurality of reference cells respectively corresponding to the first plurality of sense lines, each reference cell including a resistance element and a switching element for establishing a resistive connection between the resistance element and the corresponding sense line when one of the second plurality of word lines is addressed, and a second plurality of reference cells respectively corresponding to the second plurality of sense lines, each reference cell including a resistance element and a switching element for establishing a resistive connection between the resistance element and the corresponding sense line when one of the first plurality of word lines is addressed. In a first matrix array of memory cells, each memory cell is located on an intersection of a corresponding one of the first plurality of word lines and a corresponding one of the first plurality of sense lines, each memory cell including a magnetoresistance element and a switching element for establishing a connection between the corresponding sense line and the magnetoresistance element when the corresponding word line is addressed. In a second matrix array of memory cells, each memory cell is located on an intersection of a corresponding one of the second plurality of word lines and a corresponding one of the second plurality of sense lines, each memory cell including a magnetoresistance element and a switching element for establishing a connection between the corresponding sense line and the magnetoresistance element when the corresponding word line is addressed, A first plurality of sense circuits respectively correspond to the first plurality of sense lines, each sense circuit including a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and discharging energy stored in the capacitive element when the corresponding sense line is addressed, and a second plurality of sense circuits respectively corresponding to the second plurality of sense lines, each sense circuit including a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and removing the voltage when the corresponding sense line is addressed for discharging energy from the capacitive element when the corresponding sense line is addressed. A first plurality of voltage control elements are respectively connected in the first plurality of sense lines for maintaining the first plurality of sense lines at constant lower voltages regardless of higher voltages respectively produced by the first plurality of sense circuits. A second plurality of voltage control elements are respectively connected in the second plurality of sense lines for maintaining the second plurality of sense lines at constant lower voltages regardless of higher voltages respectively produced by the second plurality of sense circuits. A plurality of differential amplifiers may be provided so that each of the differential amplifiers produces an output voltage representative of the difference between a voltage developed across the capacitive element of a corresponding one of the first plurality of sense circuits and a voltage developed across the capacitive element of a corresponding one of the second plurality of sense circuits.
According to a fourth aspect, the present invention provides a magnetic random access memory comprising a plurality of word lines, a plurality of sense lines, a matrix array of memory cells, each memory cell being located on an intersection of a corresponding one of the word lines and a corresponding one of the sense lines, each memory cell including a magnetoresistance element and a switching element which establishes a connection between the corresponding sense line and the magnetoresistance element when the corresponding word line is addressed. A plurality of sense circuits respectively correspond to the sense lines. Each sense circuit includes a first capacitive element, a first switching element for applying a voltage to the first capacitive element through a first circuit node, a second capacitive element, a second switching element for applying a voltage to the second capacitive element through a second circuit node, and a third switching element for exclusively connecting one of the first circuit node and the second circuit node to the corresponding sense line. A column decoder selectively addresses the sense lines, the column decoder being responsive to control signals from a timing controller for controlling the first, second and third switching elements of one of the sense circuits corresponding to the addressed sense line for discharging energy stored in the first capacitive element of the one sense circuit and discharging energy stored in the second capacitive element of the one sense circuit. A row decoder selectively addresses the word lines. A write circuit initially sets one of the memory cells addressed by the column and row decoders in one of high and low resistance states depending on information to be stored therein. The write circuit is responsive to a control signal from the timing controller for setting the one memory cell in a reference resistance state after energy is discharged from the first capacitive element. A plurality of voltage control elements are respectively connected in the sense lines for maintaining the sense lines at constant lower voltages regardless of higher voltages respectively produced by the sense circuits. A plurality of differential amplifiers may be provided corresponding to the sense circuits. Each differential amplifier may be connected to the first and second circuit nodes of the corresponding sense circuit for producing a voltage representative of the difference between voltages developed at the first and second circuit nodes.